Altium

Design Rule Verification Report

Date:		2026/7/16
Time:		21:12:25
Elapsed Time:		00:00:00
Filename:		C:\Project\polaris\rk3506_hw\PCB1.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=10mil) (InNetClass('Signal')),(InNetClass('Signal'))	0
Clearance Constraint (Gap=7mil) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=5.9mil) (Max=6.2mil) (Preferred=5.9mil) (InNetClass('Signal'))	0
Width Constraint (Min=8mil) (Max=50mil) (Preferred=10mil) (InNetClass('PWR'))	0
Routing Topology Rule(Topology=Shortest) (All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Hole Size Constraint (Min=1mil) (Max=2000mil) (All)	0
Hole To Hole Clearance (Gap=0mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)	0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All)	0
Silk to Silk (Clearance=10mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	0